The present invention relates to a circuit which causes a differential op-amp common-mode output level to track a DACs common-mode level, and in particular to such circuits for use in a pipeline analog-to-digital converter (ADC).
In fully differential circuits, it is desirable to avoid variations in the common-mode component of differential signals. This is especially true in high resolution ADCs. A 1.5b/stage pipeline ADC, typically uses a switched digital-to-analog converter (DAC) in each stage to supply the required reference voltages that are used in the algorithm for the given stage. This switched DAC reference voltage is applied to the input of an op-amp. The op-amp is biased to accept a common-mode input at the same level as the common-mode output level of the previous stage. In addition, the op-amp typically has a limited common-mode rejection ratio (CMRR), and common-mode input range (CMIR). To minimize the variation in the common-mode component of these two inputs, it would be helpful to have the common-mode output level of the previous stage track the common-mode level of the DAC. Further, it would be helpful if this tracking function could be done without requiring any additional external decoupling capacitors. (Two decoupling capacitors are usually required for a positive DAC reference voltage (Vdacp) and a negative DAC reference voltage (Vdacn)). Also, it is helpful for this circuit to be insensitive to wire resistance, and for this circuit to track any high frequency variations in the common-mode DAC voltage.